In recent years, the capacity of memory devices, such as dynamic random access memories (DRAMs), has substantially increased. As just one example, DRAMs having capacities of 16 Megabits (Mb) and 64 Mb are widely used. With drastic increases in memory capacity, such as those described above, there can be an increase in the number of defects in such semiconductor storage devices.
One way to address defects in a semiconductor storage device is to include a word line redundancy circuit. A word line redundancy circuit can include a previously prepared redundant word line that can replace a defective word line.
To better understand the embodiments of the present invention, a configuration of a 64 Mb memory cell array of a 64 Mb DRAM will be described with reference to FIG. 5. The memory cell array 500 can include four banks (shown as Banks A to D) having the same structure, and including a memory capacity of 16 Mb.
Bank A is shown to include sub-banks A1 and A2 having the same layout configuration, and a memory capacity of 8 Mb. Sub-bank A1 is shown to include input/output (I/O) units 502, each having a capacity of 2 Mb and including 8 plates. One plate within each I/O unit 502 is shown as item 504. Bank A is shown to further include redundancy main-word drive circuit 506 and redundancy selection control circuit 508.
Next, methods for selecting banks (such as Banks A-D), sub-banks (such as A1 and A2) and plates (such as 504) will now be described with reference to FIGS. 6 and 7.
Banks A-D can be selected by addresses X12 and X13, as shown in Table 1. Sub-banks A1-D1 or A2-D2 can be selected by an address X10, as shown in Table 2. It is understood that sub-banks A1 and A2 can be sub-banks within Bank A, sub-banks B1 and B2 can be sub-banks within Bank B, sub-banks C1 and C2 can be sub-banks within Bank C, and sub-banks D1 and D2 can be sub-banks within Bank D.
TABLE 1 ______________________________________ X12 X13 Bank ______________________________________ 0 0 A 1 0 B 0 1 C 1 1 D ______________________________________
TABLE 2 ______________________________________ X1O A1/A2 B1/B2 C1/C2 D1/D2 ______________________________________ 0 A1 B1 C1 D1 1 A2 B2 C2 D2 ______________________________________
FIG. 6 includes 8 plates 600a to 600h (such as those shown 502 in FIG. 5) that may be included in an I/O unit (such as those shown as 502 in FIG. 5). The 8 plates (600a to 600h) can be selected by addresses X8, X9, and X11, as shown in Table 3.
TABLE 3 ______________________________________ X11 X9 X8 Plate number ______________________________________ 0 0 0 600a 0 0 1 600b 0 1 0 600c 0 1 1 600d 1 0 0 600e 1 0 1 600f 1 1 0 600g 1 1 1 600h ______________________________________
Referring back to FIG. 5, the plates 504 identified with oblique lines illustrated how four plates may be selected at one time. For example plates 504 may correspond to a plate 600a in four I/O units. In a similar fashion, another plate (600b600h) may be selected from multiple I/O groups by addresses X8, X9 and X11.
Next, a plate 700 (such as that shown as 504 or 600a-600h), and a redundancy main-word drive circuit 702 disposed in contact with a plate 700, will be described with reference to FIG. 7.
A plate 700 can include a 256K cells 704 and 706, a column redundancy circuit 708, row redundancy circuit 710. 256K cells (704 and 706) can store 256K (256.times.1024) A column redundancy circuit 708 can replace a defective digit line within 256K cells and 706) with a redundant digit line. A row redundancy circuit 710 can replace a defective word line in 256K cells (704 and 706), and/or a defective memory cell connected to a word line.
As shown in FIG. 7, a plate 700 can include main word lines W1 to W32 disposed within 256K cells 704 and 706. A main word line (W1 to W32) can drive eight sub-word lines. Therefore, 256K cells (704 and 706) can be driven by 256 sub-word lines (32.times.8 sub-word lines).
Further, 256K cells (704 and 706) can include 1024 digit line pairs arranged in a column direction. In such a particular arrangement, memory cells within 256K cells (704 and 706) may be selected by 256 sub-word lines and 1024 digit line pairs.
A row redundancy circuit 710 can be configured to include five redundancy sub-word drivers 712a-712e. A single redundancy main word line 714 can be connected to the redundancy sub-word drivers (712a-712e). Redundancy sub-word lines can be connected, two by two, to the redundancy sub-word drivers (712a-712e). Redundancy sub-word lines can extend in a +Y and -Y direction as shown in FIG. 7, with opposing sub-word lines having the shape of a comb. Furthermore, redundancy memory cells (not shown), for replacing defective memory cells, can be connected to redundancy sub-word lines.
A redundancy main-word drive circuit 702 can include 32 (8.times.4) redundancy main-word drivers 716. As one example, a redundancy main-word driver 716 can be capable of driving a redundancy main-word line (such as 714) in each plate of a sub-bank. A redundancy main-word drive circuit 702 can further include a plate decoder 718. A plate decoder 718 can receive addresses X8, X9 and X11 and generate a plate selecting signal that can select a plate, including a redundancy main-word driver 716 within the selected plate.
Referring now to FIGS. 7-10, a more detailed description of a redundancy main-word drive circuit 702 and a row redundancy circuit 710 will be given. In addition, a description will be given for a redundancy selection control circuit (shown as 1000 in FIG. 10). A redundancy selection control circuit can select redundancy sub-word lines (shown as Sw(1,0) to Sw(5,2)) that can be connected to redundancy sub-word drivers (such as 712a-712e).
In FIG. 10, sub-word lines are designated as Sw(m,n), where m can represent a particular redundancy sub-word driver (such as 712a-712e in FIGS. 7 and 10) (a vertical position) and m=1-5. The value n can represent a horizontal position and have a value of 0-3. In one particular case, a right end position, with respect to the orientation of FIG. 10, can be indicated by n=0 and a left end position, with respect to the orientation of FIG. 10, can be indicated by n=3.
Initially, a redundancy main-word drive circuit (such as 702) will be described. As noted above, a redundancy main-word drive circuit can decode addresses (such as X8, X9 and X11) with a plate decoder (such as 718) and generate a plate selecting signal. A plate selecting signal can activate a redundancy main word line (such as 714). In one particular arrangement, decode addresses X8, X9 and X11 can activate one of eight main word lines.
Referring now to FIG. 8, one example of the internal circuit of a redundancy main- word driver (such as 716) is set forth in a circuit diagram. A redundancy main-word driver is designated by the general reference character 800. Also included in FIG. 8 is a plate decoder 802. A main-word driver 800 may include a p-channel transistor P1 and an n-channel transistor N1. P-channel transistor P1 can have a source connected to a boot power source Vboot and a gate connected to a plate selecting signal PSe1. A boot power supply source Vboot can provide a potential that may be higher than a high power supply potential. A plate selecting signal PSe1 may be generated from a plate decoder 802. N-channel transistor N1 can have a source that is connected to a low power source (grounded, for example), a drain that is connected to the drain of p-channel transistor P1, and a gate that can receive the plate selecting signal PSe1. The drain-drain connection of p-channel transistor P1 and n-channel transistor N1 can be connected to a redundancy main word line 804.
Referring again to FIG. 8, when plate selecting signal PSe1 is high, n-channel transistor N1 can turn on and a redundancy main-word line 804 can go low, and be deactivated. When plate selecting signal PSe1 is low, p-channel transistor P1 can turn on and a redundancy main-word line 804 can go high (to Vboot in this particular example), and be activated.
Referring now to FIG. 9, a redundancy sub-word driver (such as 712a to 712e in FIG. 7) will be described. A redundancy sub-word driver is designated by the general reference character 900 in FIG. 9.
A redundancy sub-word driver 900 can include n-channel transistors N2 and N4 and n-channel transistors N3 and N5. N-channel transistors N2 and N4 can have gates connected to a boot power source Vboot and drains connected to a main-word line 902. The sources of transistors N2 and N4 can be connected to the gates of transistors N3 and N5, respectively. N-channel transistors N3 and N5 can have drains connected to the output terminals of sub-word selecting circuits (shown as 1002-1 to 1002-4 in FIG. 10). The source of n-channel transistor N3 can be connected to redundancy sub-word lines Sw(m, n, up) and Sw(m, n, down), and the source of n-channel transistors N5 can be connected to redundancy sub-word lines Sw(m, n+2, up) and Sw(m, n+2, down). Up and down directions are illustrated by arrows in FIG. 9.
In the arrangement illustrated by FIGS. 9 and 10, redundancy sub-word lines Sw(m,n,up) and Sw(m,n,down) can represent redundancy sub-word lines disposed in an up and down direction with respect to nodes (shown as node1 and node2 in FIG. 9) of sub-word lines Sw(m,n).
It is noted that in the particular arrangement of FIG. 10, for redundancy sub-word lines Sw(1,0) and Sw(1,2), there are no redundancy sub-word lines in the "up" direction. Also, for redundancy sub-word lines Sw(5,0) and Sw(5,2), there are no redundancy sub-word lines in the "down" direction.
Referring once again to FIG. 9, the operation of a redundancy sub-word driver 900 will be described.
When redundancy main-word line 902 is low, transistors N2-N5 can be turned off, independent of output signals from sub-word selecting circuits. Therefore, redundancy sub- word lines Sw(m,n,up) to Sw (m,n+2,down) can be inactive.
If a redundancy main-word line 902 rises to a boot power source voltage, n-channel transistors N2 to N5 can turn on. An output voltage from sub-word selecting circuits can be connected from the drains of transistors N3 and N5 to nodes node1 and node2, respectively.
As just one example, the output terminals of sub-word selecting circuits connected to n-channel transistor N3 can be high (at the boot power source voltage) while the output terminals of sub-word selecting circuits connected to n-channel transistor N5 can be low (at ground). When redundancy main-word line 902 is activated, redundancy sub-word lines Sw(m,n,down) and Sw(m,n,up) can be activated (high), while redundancy sub-word lines Sw(m,n+2,down) and Sw(m,n+2,up) can be deactivated (at a ground potential).
Thus, in the arrangement illustrated, active and inactive states of the redundancy sub-word lines Sw(m,n) can be controlled by the activation and deactivation of a redundancy main-word line 902 and the voltage of the output nodes of sub-word selecting circuits (such as 1002-1 to 1002-4 in FIG. 10).
One skilled in the art would recognize that n-channel transistors N3 and N5 can provide controllable impedance paths to redundancy sub-word lines Sw(m,n,up/down) and Sw(m, n+2, up/down). Such controllable impedance paths can be controlled by a main-word line potential. Further, activating potentials can be provided to redundancy sub-word lines Sw(m,n,up/down) and Sw(m, n+2, up/down) by way of the controllable impedance paths.
As shown in FIG. 10, a semiconductor storage device with a redundancy circuit can include a redundancy selection control circuit 1000 that includes sub-word line selecting circuits 1002-1 to 1002-4, a plate decoder 1004 and a fuse circuit 1006. Also included is a redundancy main-word drive circuit 1008 that can activate a selected redundancy main-word line 1010. A redundancy main-word line 1010 can activate selected sub-word lines Sw(1,0) to Sw(5,2) in a row redundancy circuit 1012. Sub-word lines Sw(1,0) to Sw(5,2)) can be activated and deactivated by redundancy sub-word line drivers 1014a to 1014e. Redundancy sub-word line drivers 1014a to 1014e may correspond to redundancy sub-word line drivers 712a to 712e shown in FIG. 7.
Also shown by FIG. 10, a redundancy main-word drive circuit 1008 can include a plate decoder 1016 and redundancy main-word drivers 1018.
Within redundancy selection control circuit 1000, a plate decoder 1004 can generate a plate selecting signal PSe2 from addresses X8, X9 and X10. A fuse circuit 1006 can include a number of fuses that can be opened according to a defective address (an address corresponding to a main word line that is to be replaced). According to a plate selecting signal PSe2, a precharge signal PRC, and address selecting signals (XP1 to XPj), a fuse circuit 1006 can generate fuse output signals H1 and H2. Sub-word selecting circuits (1002-1 to 1002-4) can receive fuse output signals H1 and H2 and sub-word selecting signals XN and XT and generate redundancy sub-word selecting signals S1 to S4. Redundancy sub-word selecting signals S1 to S4 can select sub-word lines Sw(1,0) to Sw(5,2).
Next, the operation of redundancy selection control circuit 1000 will be described.
Initially, a redundancy main-word driver 1008 can receive addresses X8, X9 and X11, and activate a redundancy main-word line 1010.
Fuse circuit 1006 can include a number of fuses that can be opened according to the address selecting signals of defective sub-word lines in 256K cells (such as 704 and 706 in FIG. 7). Such a setting of fuse values can be performed when a memory test is made on a semiconductor device while it is in wafer form, as just one example.
In a semiconductor memory device having a redundancy circuit, such as that set forth in FIG. 10, if a pre-charge signal PRC is activated, fuse circuit 1006 can be activated. If an activated plate selecting signal PSe2 and address selecting signals (XP1 to XPj) correspond to a defective address, fuse circuit 1006 can generate fuse output signals H1 and H2 for sub-word selecting circuits 1002-1 to 1002-4 that can replace a defective sub-word line.
Next, sub-word selecting circuits 1002-1 to 1002-4 can place redundancy sub-word selecting signals S1-S4 into an active or inactive state according to fuse output signals H1 and H2 and sub-word selecting signals XN and XT. In this arrangement, if both signals received by a sub-word selecting circuit (1002-1 to 1002-4) are active, a corresponding redundancy sub-word line selecting signal S1 to S4 can be activated. If one of the signals received by a sub-word selecting circuit (1002-1 to 1002-4) is inactive, a corresponding redundancy sub-word line selecting signal S1 to S4 can be deactivated.
Referring now to FIGS. 10 and 11a to 11e, a method of selecting redundancy sub- word lines Sw(1,0) to Sw(5,2) according to redundancy sub-word selecting signals S1-S4 will be described. In the following description it is assumed that redundancy main-word line 1010 connected to the illustrated row redundancy circuit 1012 has been activated.
FIG. 11a illustrates an example of the selection of sub-word lines Sw(1,0) to Sw(5,0) in the case where redundancy sub-word selecting signal S1 is activated, while the remaining redundancy sub-word selecting signal S2-S4 are inactive. Redundancy sub-word selecting signal S1 has been received by redundancy sub-word drivers 1014a, 1014c and 1014e, within a row redundancy circuit 1012, resulting in redundancy sub-word lines to the right (in FIGS. 10 and 11a-11e) being activated (redundancy sub-word lines Sw(1,0), Sw(3,0) and Sw(5,0)). Activated redundancy sub-word lines are shown as thick lines in FIG. 11a.
FIG. 11b shows a case where redundancy sub-word selecting signal S2 is activated, while the remaining redundancy sub-word selecting signal S1, S3 and S4 are inactive. FIG. 11c shows a case where redundancy sub-word selecting signal S3 is activated, while the remaining redundancy sub-word selecting signal S1, S2 and S4 are inactive. FIG. 11d shows a case where redundancy sub-word selecting signal S4 is activated, while the remaining redundancy sub-word selecting signal S1 to S3 are inactive. Active redundancy sub-word lines are shown by thick lines.
FIG. 11e shows a case where redundancy sub-word line signals S1, S2 and S4 are activated while redundancy sub-word line S3 is inactive. As in the cases above, active redundancy sub-word lines are shown by thick lines. It is noted that the disclosed approach allows the selection of redundancy sub-word lines according to the cases shown in FIGS. 11a-11d, and FIG. 11e shows redundancy sub-word lines that are activated at different times.
Referring now to FIG. 12a, a diagram is set forth illustrating internal circuits of 256K cells (such as those shown as 704 and 706). Such internal circuits can include sub-word drivers 1200-1a to 1200-5a and 1200-1b to 1200-5b. Sub-word drivers 1200-2a to 1200-4a and 1200-2b to 1200-4d can include two sub-word lines wired in the up and down directions (in FIG. 12a). Sub-word drivers 1200-1a and 1200-1b can include two sub-word lines wired in the down direction, and sub-word drivers 1200-5a and 1200-5b can include two sub-word lines wired in the up direction.
FIGS. 12a and 12b can illustrate how a defective sub-word line can be replaced by a conventional redundancy sub-word line approach. Referring again to FIG. 12a, assume that right sub-word line Sw1 of sub-word driver 1200-3b and left sub-word line Sw2 of sub-word driver 1200-1b are defective. FIG. 12b shows how redundancy sub-word lines in the previously described row redundancy circuit can be activated to replace defective sub-word lines Sw1 and Sw2.
In particular, in accordance with defective sub-word line Sw1, redundancy sub-word lines Sw(1,0), Sw(3,0) and Sw(5,0) can be activated. In accordance with defective sub-word line Sw2, redundancy sub-word lines Sw(1,2), Sw(3,2) and Sw(5,2) can be activated.
In the above-described semiconductor memory with a redundancy circuit, a defective sub-word line in 256K cells (such as 704 and 706) can be replaced with redundancy sub-word lines Sw(1,0) to Sw(5,2) in a row redundancy circuit (such as 1012). As shown in FIGS. 12a and 12b, a defective sub-word line is replaced by activating four redundancy sub-word lines. A drawback to such an approach is that all the redundancy sub-word lines in a vertical direction (in the view of FIGS. 12a and 12b) are used to replace one defective sub-word line.
That is, as shown in FIG. 12a, in order to replace defective sub-word line Sw(D, redundancy sub-word lines Sw(1,0), Sw(3,0) and Sw(5,0) are all used. Although defective sub-word line Sw1 ought to be replaced with a single redundancy sub-word line Sw(3,0), a redundancy selection control circuit (such as 1000 of FIG. 10) cannot control redundancy sub-word lines independently. Therefore, redundancy sub-word lines for recovering defective sub-word lines are not used effectively in such a conventional approach.